PERFORMANCE ANALYSIS OF FULLY DEPLETED DUAL MATERIAL GATE (DMG) SOI MOSFET AT 25NM TECHNOLOGY
نویسندگان
چکیده
منابع مشابه
Performance Analysis of Fully Depleted Dual Material Double Gate SOI MOSFET
Nowadays, the development of VLSI technology is mainly directed towards the miniaturization of semiconductor devices which in turn is heavily dependent on the advancement in the CMOS technology. The minimum dimension of a single device for present day technology is below sub-100 nm in channel length. As CMOS technology dimensions are being aggressively scaled down to the fundamental limits (suc...
متن کاملAnalytical Modeling and Simulation of Short-channel Effects in a Fully Depleted Dual-material Gate (dmg) Soi Mosfet
Silicon-on-insulator (SOI) has been the forerunner of the CMOS technology in the last decade offering superior CMOS devices with higher speed, higher density, excellent radiation hardness and reduced second order effects for submicron VLSI applications. Recent experimental studies have invigorated interest in fully depleted (FD) SOI devices because of their potentially superior scalability rela...
متن کاملMetal Gate Technology for Fully Depleted SOI CMOS
This paper reviews recent approaches in the development of a tunable work function metal gate CMOS technology and describes the application of one such approach to the fabrication of metal gate fullydepleted (FD) SOI transistor structures such as the ultra-thin body (UTB) FET and the FinFET.
متن کاملPerformance of Double Gate SOI MOSFET
The physical dimensions of bulk MOSFETs have been aggressively scaled down and these conventional devices will soon be experiencing limited improvements due to the scaling down. In order to continue performance improvements, new device architectures are needed. As the scaling of MOSFET into sub-100nm regime, SOI and DG-MOSFET are expect to replace traditional bulk MOSFET. These novel MOSFET dev...
متن کاملImpact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET
This study investigates the effects of oxide traps induced by SOI of various thicknesses (TSOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also in...
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ژورنال
عنوان ژورنال: International Journal of Research in Engineering and Technology
سال: 2014
ISSN: 2321-7308,2319-1163
DOI: 10.15623/ijret.2014.0319010